-
公开(公告)号:US11004930B2
公开(公告)日:2021-05-11
申请号:US16219225
申请日:2018-12-13
Applicant: Tessera, Inc.
Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia
IPC: H01L21/768 , H01L23/48 , H01L49/02 , H01L21/02
Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.
-
公开(公告)号:US09620437B2
公开(公告)日:2017-04-11
申请号:US15047295
申请日:2016-02-18
Applicant: Tessera, Inc.
Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
IPC: H01L23/48 , H01L21/768 , H01L23/498 , H01L21/78 , H01L23/14 , H01L23/00
CPC classification number: H01L23/481 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76898 , H01L21/78 , H01L23/145 , H01L23/147 , H01L23/49827 , H01L24/11 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/89 , H01L24/92 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/13099 , H01L2224/16225 , H01L2224/16235 , H01L2224/83 , H01L2224/9202 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01061 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
Abstract: A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.
-
公开(公告)号:US09362203B2
公开(公告)日:2016-06-07
申请号:US14499162
申请日:2014-09-27
Applicant: Tessera, Inc.
Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
IPC: H01L23/48 , H01L21/768 , H01L25/065 , H01L25/00 , H01L23/00 , H01L23/50
CPC classification number: H01L23/481 , H01L21/76898 , H01L23/50 , H01L24/03 , H01L24/05 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/06181 , H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2924/01322 , H01L2924/07811 , H01L2924/12042 , H01L2924/14 , H01L2924/00012 , H01L2924/00
Abstract: A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad.
Abstract translation: 制造半导体组件的方法可以包括提供具有前表面,后表面和多个导电焊盘的半导体元件,形成至少一个至少通过相应的一个导电焊盘延伸的孔, 形成从所述后表面至少部分地延伸半导体元件的厚度的开口,使得所述至少一个孔和所述开口在前表面和后表面之间的位置相遇,以及 形成在所述后表面处暴露的至少一个导电元件以电连接到外部装置,所述至少一个导电元件在所述至少一个孔内延伸并且至少进入所述开口中,所述导电元件与相应的导电垫电连接 。
-
公开(公告)号:US20160079189A1
公开(公告)日:2016-03-17
申请号:US14934544
申请日:2015-11-06
Applicant: Tessera, Inc.
Inventor: Ilyas Mohammed , Belgacem Haba , Cyprian Emeka Uzoh , Piyush Savalia , Vage Oganesian
CPC classification number: H01L23/642 , H01G4/06 , H01L21/76898 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L25/0657 , H01L25/16 , H01L28/40 , H01L28/91 , H01L28/92 , H01L2223/6622 , H01L2924/0002 , H01L2924/00
Abstract: A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.
Abstract translation: 电容器可以包括具有第一表面的基板,远离第一表面的第二表面,以及在第一和第二表面之间延伸的通孔,第一和第二金属元件以及将第一和第二表面分离和绝缘的电容器介电层 至少在通孔内的金属元件彼此之间。 第一金属元件可以在第一表面暴露并且可以延伸到通孔中。 第二金属元件可以在第二表面处露出并且可以延伸到通孔中。 第一和第二金属元件可以电连接到第一和第二电位。 电容器介电层可以具有起伏的形状。
-
公开(公告)号:US09224649B2
公开(公告)日:2015-12-29
申请号:US14451136
申请日:2014-08-04
Applicant: Tessera, Inc.
Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
IPC: H01L23/488 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/00 , H01L25/065 , H01L25/00 , H01L23/31
CPC classification number: H01L21/76898 , H01L23/3171 , H01L23/481 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02123 , H01L2224/0215 , H01L2224/0311 , H01L2224/0332 , H01L2224/03466 , H01L2224/03602 , H01L2224/0401 , H01L2224/05009 , H01L2224/05013 , H01L2224/05014 , H01L2224/05015 , H01L2224/05022 , H01L2224/05073 , H01L2224/05186 , H01L2224/05191 , H01L2224/05548 , H01L2224/05551 , H01L2224/05552 , H01L2224/05555 , H01L2224/05564 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05578 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/06181 , H01L2225/06513 , H01L2225/06527 , H01L2225/06544 , H01L2225/06548 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/15165 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2224/81805 , H01L2924/06
Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.
Abstract translation: 微电子组件包括衬底和导电元件。 衬底可以具有小于10ppm /℃的CTE,具有不延伸穿过衬底的凹部的主表面和设置在凹部内的弹性模量小于10GPa的材料。 导电元件可以包括覆盖凹部并从由衬底支撑的锚定部分延伸的接合部分。 连接部分可以在主表面处至少部分暴露以连接到微电子单元外部的部件。
-
6.
公开(公告)号:US20150249037A1
公开(公告)日:2015-09-03
申请号:US14708989
申请日:2015-05-11
Applicant: Tessera, Inc.
Inventor: Vage Oganesian , Belgacem Haba , Craig Mitchell , Ilyas Mohammed , Piyush Savalia
IPC: H01L21/768 , H01L25/00 , H01L25/11
CPC classification number: H01L21/76819 , H01L21/76877 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/4985 , H01L23/5389 , H01L24/18 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/117 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/24227 , H01L2224/24247 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/82 , H01L2224/92244 , H01L2224/97 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01061 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/07811 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15156 , H01L2924/15165 , H01L2924/15192 , H01L2924/15311 , H01L2924/15313 , H01L2924/15331 , H01L2924/157 , H01L2924/15788 , H01L2924/18161 , Y10T29/49002 , H01L2224/81 , H01L2924/00 , H01L2224/83
Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.
Abstract translation: 微电子单元可以包括具有前表面,远离前表面的后表面和在前表面具有开口的凹部和位于载体结构的前表面下方的内表面的载体结构。 微电子单元还可以包括具有邻近内表面的顶表面,远离顶表面的底表面和在顶表面处的多个触点的微电子元件。 微电子单元还可以包括与微电子元件的触点电连接的端子。 端子可以与载体结构电绝缘。 微电子单元还可以包括至少与微电子元件的底表面接触的电介质区域。 电介质区域可以限定与载体结构的前表面共面或平行的平面。
-
7.
公开(公告)号:US20150236002A1
公开(公告)日:2015-08-20
申请号:US14623161
申请日:2015-02-16
Applicant: Tessera, Inc.
Inventor: Belgacem Haba , Ilyas Mohammed , Piyush Savalia
IPC: H01L25/18 , H01L23/02 , H01L23/00 , H01L23/367 , H01L23/538
CPC classification number: H01L25/18 , H01L23/02 , H01L23/13 , H01L23/367 , H01L23/3675 , H01L23/49827 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48106 , H01L2224/48227 , H01L2224/48235 , H01L2224/48465 , H01L2224/73203 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/07811 , H01L2924/09701 , H01L2924/1431 , H01L2924/1434 , H01L2924/15159 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/20645 , H05K3/303 , H05K2201/10159 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.
Abstract translation: 微电子组件可以包括具有第一和第二表面的衬底,覆盖在第一表面上的至少两个逻辑芯片,以及存储器芯片,其具有在其上的触点的前表面,存储芯片的前表面面对每个逻辑芯片的后表面 。 衬底可以具有导电结构,并且端子在第二表面处暴露以与部件连接。 每个逻辑芯片的信号触点可以通过衬底的导电结构直接电连接到其他逻辑芯片的信号触点,用于在逻辑芯片之间传输信号。 逻辑芯片可以适于同时执行一个给定的进程线程的一组指令。 存储器芯片的触点可以通过衬底的导电结构直接电连接到至少一个逻辑芯片的信号触点。
-
公开(公告)号:US20150140807A1
公开(公告)日:2015-05-21
申请号:US14610300
申请日:2015-01-30
Applicant: Tessera, Inc.
Inventor: Ilyas Mohammed , Belgacem Haba , Cyprian Emeka Uzoh , Piyush Savalia
IPC: H01L21/768
CPC classification number: H01L21/76877 , H01L21/486 , H01L21/76837 , H01L21/76898 , H01L23/147 , H01L23/15 , H01L23/481 , H01L23/49827 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
Abstract: A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.
Abstract translation: 微电子单元可以包括其中具有前表面和后表面的基板和其中的有源半导体器件,所述基板具有布置成在后表面的区域上的对称或不对称分布的多个开口,连接到第一和第二导电通孔的第一和第二导电通孔 在前表面暴露的焊盘,在相应的一个开口内延伸的多个第一和第二导电互连,以及暴露以与外部元件互连的第一和第二导电触点。 多个第一导电互连可以通过所述多个开口中的至少一个与所述多个第二导电互连部分开,所述至少一个开口至少部分地填充有绝缘材料。 开口的分布可以包括在第一方向上间隔开的至少m个开口和在横向于第一方向的第二方向上间隔开的n个开口。
-
9.
公开(公告)号:US20140357021A1
公开(公告)日:2014-12-04
申请号:US14461919
申请日:2014-08-18
Applicant: Tessera, Inc.
Inventor: Belgacem Haba , Ilyas Mohammed , Piyush Savalia
IPC: H01L25/00 , H01L25/065 , H05K3/30
CPC classification number: H01L25/18 , H01L23/02 , H01L23/13 , H01L23/367 , H01L23/3675 , H01L23/49827 , H01L23/5386 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32245 , H01L2224/33181 , H01L2224/48106 , H01L2224/48227 , H01L2224/48235 , H01L2224/48465 , H01L2224/73203 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/07811 , H01L2924/09701 , H01L2924/1431 , H01L2924/1434 , H01L2924/15159 , H01L2924/15174 , H01L2924/15184 , H01L2924/15192 , H01L2924/15311 , H01L2924/18161 , H01L2924/20645 , H05K3/303 , H05K2201/10159 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.
Abstract translation: 微电子组件可以包括具有第一和第二表面的衬底,覆盖在第一表面上的至少两个逻辑芯片,以及存储器芯片,其具有在其上的触点的前表面,存储芯片的前表面面对每个逻辑芯片的后表面 。 衬底可以具有导电结构,并且端子在第二表面处暴露以与部件连接。 每个逻辑芯片的信号触点可以通过衬底的导电结构直接电连接到其他逻辑芯片的信号触点,用于在逻辑芯片之间传输信号。 逻辑芯片可以适于同时执行一个给定的进程线程的一组指令。 存储器芯片的触点可以通过衬底的导电结构直接电连接到至少一个逻辑芯片的信号触点。
-
10.
公开(公告)号:US08835223B2
公开(公告)日:2014-09-16
申请号:US14162011
申请日:2014-01-23
Applicant: Tessera, Inc.
Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Craig Mitchell , Piyush Savalia
IPC: H01L29/788 , H01L23/00 , H01L23/538
CPC classification number: H01L24/80 , H01L21/6835 , H01L21/76805 , H01L21/76898 , H01L23/481 , H01L23/5384 , H01L24/02 , H01L24/24 , H01L24/25 , H01L24/27 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68372 , H01L2224/0231 , H01L2224/0235 , H01L2224/02371 , H01L2224/2401 , H01L2224/2405 , H01L2224/24146 , H01L2224/244 , H01L2224/2512 , H01L2224/32225 , H01L2224/82005 , H01L2224/821 , H01L2224/82106 , H01L2224/83005 , H01L2224/83191 , H01L2224/8385 , H01L2224/92 , H01L2224/9202 , H01L2224/92244 , H01L2224/93 , H01L2224/94 , H01L2225/06544 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2224/27 , H01L2224/83 , H01L2224/82 , H01L2924/00
Abstract: An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element.
Abstract translation: 提供了组装和制造方法。 可以通过将覆盖在第一半导体元件的主表面上的第一导电元件与暴露在第二半导体元件的前表面处的导电焊盘并置来形成该组件。 可以形成延伸穿过第二半导体元件的导电焊盘并露出第一导电元件的表面的开口。 开口可替代地形成为延伸穿过第一导电元件。 第二导电元件可以形成为至少在开口内延伸并且电接触导电垫和第一导电元件。 第三半导体元件可以相对于第二半导体元件以类似的方式定位。
-
-
-
-
-
-
-
-
-