Invention Grant
- Patent Title: Dielectric filler fins for planar topography in gate level
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Application No.: US14808914Application Date: 2015-07-24
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Publication No.: US09245981B2Publication Date: 2016-01-26
- Inventor: Kangguo Cheng , Ramachandra Divakaruni , Bruce B. Doris , Ali Khakifirooz , Edward J. Nowak , Kern Rim
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/06

Abstract:
An array of stacks containing a semiconductor fins and an oxygen-impermeable cap is formed on a semiconductor substrate with a substantially uniform areal density. Oxygen-impermeable spacers are formed around each stack, and the semiconductor substrate is etched to vertically extend trenches. Semiconductor sidewalls are physically exposed from underneath the oxygen-impermeable spacers. The oxygen-impermeable spacers are removed in regions in which semiconductor fins are not needed. A dielectric oxide material is deposited to fill the trenches. Oxidation is performed to convert a top portion of the semiconductor substrate and semiconductor fins not protected by oxygen-impermeable spacers into dielectric material portions. Upon removal of the oxygen-impermeable caps and remaining oxygen-impermeable spacers, an array including semiconductor fins and dielectric fins is provided. The dielectric fins alleviate variations in the local density of protruding structures, thereby reducing topographical variations in the height of gate level structures to be subsequently formed.
Public/Granted literature
- US20150333156A1 DIELECTRIC FILLER FINS FOR PLANAR TOPOGRAPHY IN GATE LEVEL Public/Granted day:2015-11-19
Information query
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