Invention Grant
US09281043B1 Resistive memory write circuitry with bit line drive strength based on storage cell line resistance
有权
具有基于存储单元线路电阻的位线驱动强度的电阻式存储器写入电路
- Patent Title: Resistive memory write circuitry with bit line drive strength based on storage cell line resistance
- Patent Title (中): 具有基于存储单元线路电阻的位线驱动强度的电阻式存储器写入电路
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Application No.: US14582745Application Date: 2014-12-24
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Publication No.: US09281043B1Publication Date: 2016-03-08
- Inventor: Pulkit Jain , Fatih Hamzaoglu , Liqiong Wei
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G06F12/02 ; G06F3/06
Abstract:
An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.
Information query
