Invention Grant
- Patent Title: Stacked semiconductor device
- Patent Title (中): 堆叠半导体器件
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Application No.: US13897659Application Date: 2013-05-20
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Publication No.: US09299666B2Publication Date: 2016-03-29
- Inventor: Takashi Aoki
- Applicant: CANON KABUSHIKI KAISHA
- Applicant Address: JP Tokyo
- Assignee: CANON KABUSHIKI KAISHA
- Current Assignee: CANON KABUSHIKI KAISHA
- Current Assignee Address: JP Tokyo
- Agency: Fitzpatrick, Cella, Harper & Scinto
- Priority: JP2012-122271 20120529
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L25/10 ; H01L23/498

Abstract:
A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability.
Public/Granted literature
- US20130320569A1 STACKED SEMICONDUCTOR DEVICE Public/Granted day:2013-12-05
Information query
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