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    SEMICONDUCTOR MODULE MANUFACTURING METHOD, ELECTRONIC EQUIPMENT MANUFACTURING METHOD, SEMICONDUCTOR MODULE, AND ELECTRONIC EQUIPMENT
    2.
    发明申请
    SEMICONDUCTOR MODULE MANUFACTURING METHOD, ELECTRONIC EQUIPMENT MANUFACTURING METHOD, SEMICONDUCTOR MODULE, AND ELECTRONIC EQUIPMENT 有权

    公开(公告)号：US20220102330A1

    公开(公告)日：2022-03-31

    申请号：US17545040

    申请日：2021-12-08

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Kana Onoko ,  Takashi Aoki

    IPC: H01L25/16 ,  H01L23/498 ,  H01L21/60

    Abstract: A chip component including a first electrode and a second electrode, a semiconductor device including a first land and a second land, and a printed wiring board are prepared. A first solder paste and a second solder paste are supplied to the printed wiring board. The chip component is placed on the printed wiring board so that the first electrode is in contact with the first solder paste and the second electrode is in contact with the second solder paste. The semiconductor device is placed on the printed wiring board so that the first land faces the first electrode and the second land faces the second electrode. The solder paste is heated and melted, the first land and the first electrode are bonded to each other, and the second land and the second electrode are bonded to each other.

    ELECTRONIC COMPONENT MOUNTING STRUCTURE AND PRINTED WIRING BOARD
    3.
    发明申请
    ELECTRONIC COMPONENT MOUNTING STRUCTURE AND PRINTED WIRING BOARD 有权
    电子元件安装结构和印刷电路板

    公开(公告)号：US20150173195A1

    公开(公告)日：2015-06-18

    申请号：US14558614

    申请日：2014-12-02

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Takashi Aoki ,  Yasuhiro Sawada

    IPC: H05K1/18 ,  H05K1/11

    CPC classification number: H05K1/111 ,  H05K1/0243 ,  H05K3/3442 ,  H05K2201/09272 ,  H05K2201/09427 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10651 ,  Y02P70/611

    Abstract: An electronic component mounting structure includes a first land, a second land making a pair with the first land, an electronic component having a chip shape and including a first electrode connected to the first land and a second electrode connected to the second land, a first wiring pattern connected to the first land, and a second wiring pattern connected to the second land and including a first partial pattern overlapping a portion of a body of the electronic component in planar view, the portion being not covered with the pair of electrodes, a second partial pattern formed integral with the first partial pattern and overlapping the first electrode of the electronic component in planar view, and a third partial pattern formed integral with the second partial pattern and parallel to the first wiring pattern.

    Abstract translation: 一种电子部件安装结构，包括第一焊盘，与第一焊盘成对的第二焊盘，具有芯片形状的电子部件，并且包括连接到第一焊盘的第一电极和连接到第二焊盘的第二电极，第一焊盘 连接到第一焊盘的布线图案和连接到第二焊盘的第二布线图案，并且包括在平面图中与电子部件的主体的一部分重叠的第一部分图案，该部分未被该对电极覆盖， 第二部分图案与第一部分图案整体形成并且在平面图中与电子部件的第一电极重叠，以及与第二部分图案一体形成并平行于第一布线图案的第三部分图案。

    SEMICONDUCTOR MODULE AND ELECTRONIC APPARATUS
    4.
    发明申请
    SEMICONDUCTOR MODULE AND ELECTRONIC APPARATUS 有权

    公开(公告)号：US20220386468A1

    公开(公告)日：2022-12-01

    申请号：US17826013

    申请日：2022-05-26

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Yuya Karakawa ,  Mitsutoshi Hasegawa ,  Takashi Aoki ,  Noritake Tsuboi

    IPC: H05K1/18 ,  H01L23/498 ,  H05K3/34

    Abstract: A semiconductor module includes a semiconductor device having a first land, a second land, and a third land, a wiring board having a substrate, and a fourth land, a fifth land, and a sixth land disposed on the main surface of the substrate, a chip component having a first electrode and a second electrode disposed across a distance in the longitudinal direction and being disposed between the wiring board and the semiconductor device, a first solder joint for bonding the first land, the fourth land, and the first electrode, a second solder joint for bonding the second land, the fifth land, and the second electrode, and a third solder joint for bonding the third land and the sixth land. The volume of the first solder joint and the volume of the second solder joint are each larger than the volume of the third solder joint.

    SEMICONDUCTOR DEVICE, PRINTED CIRCUIT BOARD, ELECTRONIC DEVICE, AND IMAGE PICKUP APPARATUS
    5.
    发明申请
    SEMICONDUCTOR DEVICE, PRINTED CIRCUIT BOARD, ELECTRONIC DEVICE, AND IMAGE PICKUP APPARATUS 审中-公开

    公开(公告)号：US20200051887A1

    公开(公告)日：2020-02-13

    申请号：US16524660

    申请日：2019-07-29

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Takashi Aoki

    IPC: H01L23/367 ,  H05K1/18 ,  H01L27/146 ,  H01L23/498 ,  H01L23/00

    Abstract: A semiconductor device includes a rigid substrate, a plate-like heat dissipating member, and a semiconductor element provided between the rigid substrate and the heat dissipating member and mounted on the rigid substrate. The heat dissipating member includes a first portion that defines a slit or a recess portion. The first portion extends along a first virtual line segment extending from a first side of an outer periphery of a first region that overlaps with the semiconductor element toward an outside of the first region as viewed in a direction perpendicular to a main surface of the heat dissipating member, and a length of the first portion in a direction parallel to the first side is equal to or smaller than a length of the first portion in a direction perpendicular to the first side.

    Stacked semiconductor device
    8.
    发明授权
    Stacked semiconductor device 有权
    堆叠半导体器件

    公开(公告)号：US09299666B2

    公开(公告)日：2016-03-29

    申请号：US13897659

    申请日：2013-05-20

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Takashi Aoki

    IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L23/498

    CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/3511

    Abstract: A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability.

    Abstract translation: 位于上侧的第一半导体封装包括用于封装第一半导体芯片的第一印刷线路板和封装树脂。 位于下侧的第二半导体封装包括第二印刷线路板。 第一印刷布线板包括第一焊盘和第一阻焊层，其具有用于暴露第一焊盘的第一开口。 第二印刷电路板分别包括与第一焊盘相对的第二焊盘，第二阻焊层具有用于分别暴露第二焊盘并与第一焊盘相对的第二开口。 第一焊盘和第二焊盘分别通过第一开口和第二开口彼此焊接。 第一开口的开口面积被设定为小于第二开口的开口面积。 这提高了联合可靠性。

    Semiconductor package and stacked semiconductor package
    9.
    发明授权
    Semiconductor package and stacked semiconductor package 有权
    半导体封装和堆叠半导体封装

    公开(公告)号：US08803329B2

    公开(公告)日：2014-08-12

    申请号：US13892538

    申请日：2013-05-13

    Applicant: Canon Kabushiki Kaisha

    Inventor： Takashi Aoki

    IPC: H01L23/495

    CPC classification number: H01L24/09 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A semiconductor package includes a printed wiring board and a semiconductor chip that has a first signal terminal and a second signal terminal and is mounted on the printed wiring board. The printed wiring board has a first land and a second land for solder joining, which are formed on a surface layer thereof. Further, the printed wiring board has a first wiring for electrically connecting the first signal terminal of the semiconductor chip and the first land, and a second wiring for electrically connecting the second signal terminal of the semiconductor chip and the second land. The second wiring is formed so that the wiring length thereof is larger than that of the first wiring. The second land is formed so that the surface area thereof is larger than that of the first land. This reduces difference in transmission line characteristics due to the difference in wiring length.

    Abstract translation: 半导体封装包括印刷线路板和具有第一信号端子和第二信号端子并安装在印刷线路板上的半导体芯片。 印刷电路板具有形成在其表面层上的第一焊盘和焊接用焊盘。 此外，印刷布线板具有用于将半导体芯片的第一信号端子与第一焊盘电连接的第一布线和用于电连接半导体芯片的第二信号端子和第二焊盘的第二布线。 第二布线形成为使得布线长度大于第一布线的布线长度。 形成第二焊盘的表面积大于第一焊盘的面积。 这减少了由于布线长度的差异导致的传输线特性的差异。

    STACKED SEMICONDUCTOR DEVICE
    10.
    发明申请
    STACKED SEMICONDUCTOR DEVICE 有权
    堆叠半导体器件

    公开(公告)号：US20130320569A1

    公开(公告)日：2013-12-05

    申请号：US13897659

    申请日：2013-05-20

    Applicant: CANON KABUSHIKI KAISHA

    Inventor： Takashi Aoki

    IPC: H01L23/00

    CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/3511

    Abstract: A first semiconductor package which is located on an upper side includes a first printed wiring board and an encapsulation resin for encapsulating a first semiconductor chip. A second semiconductor package which is located on a lower side includes a second printed wiring board. The first printed wiring board includes first lands and a first solder resist having first openings for exposing the first lands. The second printed wiring board includes second lands opposed to the first lands, respectively, and a second solder resist having second openings for exposing the second lands and opposed to the first openings, respectively. The first lands and the second lands are solder joined to each other through the first openings and the second openings, respectively. The opening area of the first opening is set to be smaller than the opening area of the second opening. This improves joint reliability.

    Abstract translation: 位于上侧的第一半导体封装包括用于封装第一半导体芯片的第一印刷线路板和封装树脂。 位于下侧的第二半导体封装包括第二印刷线路板。 第一印刷布线板包括第一焊盘和第一阻焊层，其具有用于暴露第一焊盘的第一开口。 第二印刷电路板分别包括与第一焊盘相对的第二焊盘，第二阻焊层具有用于分别暴露第二焊盘并与第一焊盘相对的第二开口。 第一焊盘和第二焊盘分别通过第一开口和第二开口彼此焊接。 第一开口的开口面积被设定为小于第二开口的开口面积。 这提高了联合可靠性。

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