Invention Grant
- Patent Title: Parallel bit interleaver
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Application No.: US14804466Application Date: 2015-07-21
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Publication No.: US09319072B2Publication Date: 2016-04-19
- Inventor: Mihail Petrov
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: PANASONIC CORPORATION
- Current Assignee: PANASONIC CORPORATION
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: EP11004125 20110518
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G06F11/00 ; H03M13/27 ; H03M13/11 ; H03M13/25 ; H03M13/29 ; H03M13/35 ; H04L1/00 ; H04L1/06

Abstract:
A bit interleaving method applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks of Q bits each, dividing the processed codeword into constellation words of M bits each, and applying an intra-cyclic-block permutation process to the cyclic blocks, where the codeword is divided into F×N/M folding sections of M/F cyclic blocks each and the constellation words are each associated with one of the folding sections, and the bit permutation process is applied such that the constellation words are each made up of F bits from each of M/F different cyclic blocks in the associated section, after the permutation process.
Public/Granted literature
- US20150333771A1 PARALLEL BIT INTERLEAVER Public/Granted day:2015-11-19
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