Invention Grant
- Patent Title: Memory array test logic
- Patent Title (中): 内存阵列测试逻辑
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Application No.: US14266039Application Date: 2014-04-30
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Publication No.: US09355743B2Publication Date: 2016-05-31
- Inventor: Amlan Ghosh , Keith Allen Kasprak , John Wuu , John Reginald Riley, III
- Applicant: Advanced Micro Devices Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: G11C29/02
- IPC: G11C29/02 ; G11C11/419

Abstract:
A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.
Public/Granted literature
- US20150318056A1 MEMORY ARRAY TEST LOGIC Public/Granted day:2015-11-05
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