Invention Grant
- Patent Title: Packaging substrate having embedded through-via interposer
- Patent Title (中): 具有嵌入式通孔插入器的封装基板
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Application No.: US14602645Application Date: 2015-01-22
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Publication No.: US09357659B2Publication Date: 2016-05-31
- Inventor: Dyi-Chung Hu , Tzyy-Jang Tseng
- Applicant: Unimicron Technology Corporation
- Applicant Address: TW Taoyuan
- Assignee: Unimicron Technology Corporation
- Current Assignee: Unimicron Technology Corporation
- Current Assignee Address: TW Taoyuan
- Agency: Mintz Levin Cohn Ferris Glovsky and Popeo, P.C.
- Agent Peter F. Corless; Steven M. Jensen
- Priority: TW100139667A 20111031
- Main IPC: H05K1/14
- IPC: H05K1/14 ; H05K1/16 ; H05K1/18 ; H05K3/40 ; H05K1/11 ; H01L23/14 ; H01L23/15 ; H01L21/48 ; H01L21/768 ; H01L23/498

Abstract:
A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias. As such, the first end surfaces of the conductive through-vias of the through-via interposer are electrically connected to the redistribution layer to thereby be electrically connected to electrode pads of a semiconductor chip having smaller pitches, while the second end surfaces of the conductive through-vias electrically connect with conductive vias of the built-up structure having larger pitches, thereby allowing the packaging substrate to be coupled with the semiconductor chip having high-density circuits.
Public/Granted literature
- US20150129285A1 PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER Public/Granted day:2015-05-14
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