公开(公告)号：US09460992B2

公开(公告)日：2016-10-04

申请号：US14641901

申请日：2015-03-09

Applicant: Unimicron Technology Corporation

Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu ,  Ying-Chih Chan

IPC: H01L23/498 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H05K1/11 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/115 ,  H05K2201/10378 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract translation: 提供了一种贯穿孔插入器，包括板体，形成在板体中的导电凝胶，以及布置在板体上的电路再分布结构。 导电性凝胶具有从板体的表面突出的一端，与其他结构（例如，封装基板或电路结构）接触的导电性凝胶的突出部的面积增加，从而加强 导电凝胶和插层的可靠性。

公开(公告)号：US09337136B2

公开(公告)日：2016-05-10

申请号：US14641887

申请日：2015-03-09

Applicant: Unimicron Technology Corporation

Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu ,  Ying-Chih Chan

IPC: H01L21/4763 ,  H01L23/498 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H05K1/11 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/115 ,  H05K2201/10378 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract translation: 提供了一种贯穿孔插入器，包括板体，形成在板体中的导电凝胶，以及布置在板体上的电路再分布结构。 导电性凝胶具有从板体的表面突出的一端，与其他结构（例如，封装基板或电路结构）接触的导电性凝胶的突出部的面积增大， 导电凝胶和插层的可靠性。

公开(公告)号：US09224683B2

公开(公告)日：2015-12-29

申请号：US14641918

申请日：2015-03-09

Applicant: Unimicron Technology Corporation

Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu ,  Ying-Chih Chan

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H05K1/11 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/115 ,  H05K2201/10378 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract translation: 提供了一种贯穿孔插入器，包括板体，形成在板体中的导电凝胶，以及布置在板体上的电路再分布结构。 导电性凝胶具有从板体的表面突出的一端，与其他结构（例如，封装基板或电路结构）接触的导电性凝胶的突出部的面积增加，从而加强 导电凝胶和插层的可靠性。

公开(公告)号：US20140084463A1

公开(公告)日：2014-03-27

申请号：US14095144

申请日：2013-12-03

Applicant: Unimicron Technology Corporation

Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu ,  Yu-Shan Hu

IPC: H01L21/56 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76885 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Abstract translation: 提供一种半导体封装结构，包括：具有设置在其上的电极焊盘的半导体芯片和设置在电极焊盘上的金属凸块; 封装半导体芯片的密封剂; 介电层，其形成在所述密封剂上并且具有形成在其中的多个图案化的凹凸，用于暴露所述金属凸块; 形成在电介质层的图案化凹凸中并与金属凸块电连接的布线层; 以及具有设置在其表面上的多个金属柱的金属箔，使得金属箔设置在密封剂上，金属柱穿透密封剂，以延伸到半导体芯片的非活性表面。 与现有技术相比，本发明减小了封装结构的整体厚度，提高了电传输效率并提高了散热效果。

公开(公告)号：US20150129285A1

公开(公告)日：2015-05-14

申请号：US14602645

申请日：2015-01-22

Applicant: Unimicron Technology Corporation

Inventor： Dyi-Chung Hu ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H05K1/11

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias. As such, the first end surfaces of the conductive through-vias of the through-via interposer are electrically connected to the redistribution layer to thereby be electrically connected to electrode pads of a semiconductor chip having smaller pitches, while the second end surfaces of the conductive through-vias electrically connect with conductive vias of the built-up structure having larger pitches, thereby allowing the packaging substrate to be coupled with the semiconductor chip having high-density circuits.

Abstract translation: 提供具有嵌入式通孔插入器的封装衬底，其包括密封剂层，嵌入密封层中的通孔插入件，并且其中具有多个导电通孔，重分布层嵌入密封层中并形成在 所述通孔插入件与所述导电通孔的第一端面电连接，以及形成在所述密封层和所述通孔插入件上的积层结构，用于电连接所述导电通孔的第二端面 。 因此，通孔插入器的导电通孔的第一端面电连接到再分配层，从而与具有较小间距的半导体芯片的电极焊盘电连接，而导电的第二端面 通孔与具有较大间距的积层结构的导电通孔电连接，从而允许封装衬底与具有高密度电路的半导体芯片耦合。

公开(公告)号：US20140264335A1

公开(公告)日：2014-09-18

申请号：US13845800

申请日：2013-03-18

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Dyi-Chung Hu ,  Tsung-Si Wang ,  Jui-Yang Ma

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L22/32 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package substrate is provided, including a board body having a wiring region and a testing region defined thereon, conductive pads embedded in the wiring region, and a plurality of testing pads disposed in the testing region and electrically connected to the conductive pads, wherein the top surface area of each of the testing pads is greater than the top surface area of each of the conductive pads in order to facilitate a precise alignment of a probe with a corresponding one of the testing pads and prevent the probe from being blocked by the board body when in electrically testing an embedded circuit.

Abstract translation: 提供一种封装基板，包括具有布线区域和限定在其上的测试区域的板体，嵌入布线区域中的导电焊盘以及设置在测试区域中并电连接到导电焊盘的多个测试焊盘，其中， 每个测试焊盘的顶表面积大于每个导电焊盘的顶表面积，以便于探针与对应的一个测试焊盘的精确对准，并防止探针被板阻挡 身体在电测试嵌入式电路时。

公开(公告)号：US09485863B2

公开(公告)日：2016-11-01

申请号：US13780421

申请日：2013-02-28

Applicant: Unimicron Technology Corporation

Inventor： Tzyy-Jang Tseng ,  Chung W. Ho ,  Dyi-Chung Hu ,  Huan-Ling Lee ,  Sheng-Yuah He

IPC: H05K1/05 ,  H05K3/46 ,  H05K3/10 ,  H05K1/02 ,  H01L21/56 ,  H01L23/14 ,  H01L23/498

CPC classification number: H05K1/05 ,  H01L21/568 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/02 ,  H05K1/0271 ,  H05K3/10 ,  H05K3/4644 ,  H05K3/4682 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A fabrication method of a coreless packaging substrate is provided, including the steps of: forming an inner built-up circuit board on a carrier; removing the carrier; and symmetrically forming a first outer built-up structure and a second outer built-up structure on top and bottom surfaces of the inner built-up circuit board, respectively. The present invention effectively increases the product yield, saves the fabrication cost, and reduces wastes.

Abstract translation: 提供一种无芯封装基板的制造方法，包括以下步骤：在载体上形成内层叠电路板; 移除载体; 并且分别在内部堆叠电路板的顶表面和底表面上对称地形成第一外部组合结构和第二外部组合结构。 本发明有效地提高了产品产量，节省了制造成本，并且减少了废物。

公开(公告)号：US09357659B2

公开(公告)日：2016-05-31

申请号：US14602645

申请日：2015-01-22

Applicant: Unimicron Technology Corporation

Inventor： Dyi-Chung Hu ,  Tzyy-Jang Tseng

IPC: H05K1/14 ,  H05K1/16 ,  H05K1/18 ,  H05K3/40 ,  H05K1/11 ,  H01L23/14 ,  H01L23/15 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A packaging substrate having an embedded through-via interposer is provided, including an encapsulant layer, a through-via interposer embedded in the encapsulant layer and having a plurality of conductive through-vias therein, a redistribution layer embedded in the encapsulant layer and formed on the through-via interposer so as to electrically connect with first end surfaces of the conductive through-vias, and a built-up structure formed on the encapsulant layer and the through-via interposer for electrically connecting second end surfaces of the conductive through-vias. As such, the first end surfaces of the conductive through-vias of the through-via interposer are electrically connected to the redistribution layer to thereby be electrically connected to electrode pads of a semiconductor chip having smaller pitches, while the second end surfaces of the conductive through-vias electrically connect with conductive vias of the built-up structure having larger pitches, thereby allowing the packaging substrate to be coupled with the semiconductor chip having high-density circuits.

Abstract translation: 提供具有嵌入式通孔插入器的封装衬底，其包括密封剂层，嵌入密封层中的通孔插入件，并且其中具有多个导电通孔，重分布层嵌入密封层中并形成在 所述通孔插入件与所述导电通孔的第一端面电连接，以及形成在所述密封层和所述通孔插入件上的积层结构，用于电连接所述导电通孔的第二端面 。 因此，通孔插入器的导电通孔的第一端面电连接到再分配层，从而与具有较小间距的半导体芯片的电极焊盘电连接，而导电的第二端面 通孔与具有较大间距的积层结构的导电通孔电连接，从而允许封装衬底与具有高密度电路的半导体芯片耦合。

公开(公告)号：US20140027925A1

公开(公告)日：2014-01-30

申请号：US13845625

申请日：2013-03-18

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Tzyy-Jang Tseng ,  Dyi-Chung Hu ,  Ying-Chih Chan

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/115 ,  H05K2201/10378 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/014

Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.

Abstract translation: 提供了一种贯穿孔插入器，包括板体，形成在板体中的导电凝胶，以及布置在板体上的电路再分布结构。 导电性凝胶具有从板体的表面突出的一端，与其他结构（例如，封装基板或电路结构）接触的导电性凝胶的突出部的面积增加，从而加强 导电凝胶和插层的可靠性。

公开(公告)号：US09781843B2

公开(公告)日：2017-10-03

申请号：US14602656

申请日：2015-01-22

Applicant: Unimicron Technology Corporation

Inventor： Dyi-Chung Hu ,  Tzyy-Jang Tseng

IPC: H05K3/40 ,  H05K1/18 ,  H05K1/11 ,  H05K1/14 ,  H01L23/14 ,  H01L23/15 ,  H01L21/48 ,  H01L21/768 ,  H01L23/498

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A method of fabricating a packaging substrate having an embedded through-via interposer is provided. The method includes providing a through-via interposer having opposite first and second sides and conductive through-vias in communication with the first and second sides, wherein each of the conductive through-vias has a first end surface on the first side and a second end surface on the second side, and the second end surfaces protrude below the second side to serve as conductive bumps. Next, forming a redistribution layer on the first side and the first end surfaces such that the redistribution layer electrically connects with the first end surfaces. Afterwards, forming an encapsulant layer to encapsulate and embed the through-via interposer, wherein the encapsulant layer has opposite first and second surfaces. Next, forming a built-up structure on the second surface of the encapsulant layer, the second side of the through-via interposer and the conductive bumps.