Invention Grant
US09369270B1 Dual-coupled phase-locked loops for clock and packet-based synchronization
有权
用于时钟和基于分组的同步的双耦合锁相环
- Patent Title: Dual-coupled phase-locked loops for clock and packet-based synchronization
- Patent Title (中): 用于时钟和基于分组的同步的双耦合锁相环
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Application No.: US14212598Application Date: 2014-03-14
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Publication No.: US09369270B1Publication Date: 2016-06-14
- Inventor: Menno Spijker
- Applicant: Integrated Device Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agency: Myers Bigel & Sibley
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H04L7/033 ; H03L7/07

Abstract:
A Synchronous Ethernet (SyncE) network device includes a pair of phase-locked loops including a first phase-locked loop responsive to a SyncE input clock and a second phase-locked loop coupled to the first phase-locked loop. The second phase-locked loop is configured to be simultaneously lockable to both the SyncE input clock via the first phase-locked loop and an IEEE 1588 packet stream, during a locked mode of operation, and also lockable to the SyncE input clock during a holdover mode of operation which is triggered in response to a failure of the IEEE 1588 packet stream.
Information query
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