Invention Grant
US09369270B1 Dual-coupled phase-locked loops for clock and packet-based synchronization 有权
用于时钟和基于分组的同步的双耦合锁相环

Dual-coupled phase-locked loops for clock and packet-based synchronization
Abstract:
A Synchronous Ethernet (SyncE) network device includes a pair of phase-locked loops including a first phase-locked loop responsive to a SyncE input clock and a second phase-locked loop coupled to the first phase-locked loop. The second phase-locked loop is configured to be simultaneously lockable to both the SyncE input clock via the first phase-locked loop and an IEEE 1588 packet stream, during a locked mode of operation, and also lockable to the SyncE input clock during a holdover mode of operation which is triggered in response to a failure of the IEEE 1588 packet stream.
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