A current switching cell for a digital to analog converter. The switching cell includes three stages, a first control stage, a data stage, and a second control stage. The first control stage is configured to either disconnect the outputs of the digital to analog converter, or to connect them to the outputs of the data stage. The data stage is configured to operate in one of two states, depending on a data signal received, and the second control stage is configured to selectively invert the output of the digital to analog converter. The two control stages may be driven with several combinations of control waveforms to implement a non return to zero mode, a return to zero mode, inverse non return to zero mode, and inverse return to zero mode.