Invention Grant
US09397218B2 Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devices
有权
用于减轻半导体器件中寄生电容的影响的方法和装置
- Patent Title: Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devices
- Patent Title (中): 用于减轻半导体器件中寄生电容的影响的方法和装置
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Application No.: US14567971Application Date: 2014-12-11
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Publication No.: US09397218B2Publication Date: 2016-07-19
- Inventor: Chuan-Cheng Cheng , Runzi Chang
- Applicant: Marvell World Trade Ltd.
- Applicant Address: BB St. Michael
- Assignee: Marvell World Trade Ltd.
- Current Assignee: Marvell World Trade Ltd.
- Current Assignee Address: BB St. Michael
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/423

Abstract:
Embodiments include a semiconductor device comprising: a gate layer comprising (i) a first section and (ii) a second section, wherein the gate layer is non-linear such that the first section of the gate layer is offset with respect to the second section of the gate layer; and a first contact and a second contact, wherein the first section of the gate layer is at (i) a first distance from the first contact and (ii) a second distance from the second contact, wherein the first distance is different from the second distance.
Public/Granted literature
- US20150194518A1 METHOD AND APPARATUS FOR MITIGATING EFFECTS OF PARASITIC CAPACITANCE IN SEMICONDUCTOR DEVICES Public/Granted day:2015-07-09
Information query
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