Invention Grant
US09397686B2 Method and system for a low input voltage low impedance termination stage for current inputs
有权
用于电流输入的低输入电压低阻抗终端级的方法和系统
- Patent Title: Method and system for a low input voltage low impedance termination stage for current inputs
- Patent Title (中): 用于电流输入的低输入电压低阻抗终端级的方法和系统
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Application No.: US14865582Application Date: 2015-09-25
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Publication No.: US09397686B2Publication Date: 2016-07-19
- Inventor: Rajesh Zele , Gaurav Chandra
- Applicant: Maxlinear, Inc.
- Applicant Address: US CA Carlsbad
- Assignee: Maxlinear, Inc.
- Current Assignee: Maxlinear, Inc.
- Current Assignee Address: US CA Carlsbad
- Agency: McAndrews, Held & Malloy
- Main IPC: H03M1/66
- IPC: H03M1/66 ; H03M1/70 ; H03F3/45 ; H03M1/74

Abstract:
A low input voltage low impedance termination stage for current inputs may include an output stage for an electrical circuit, the output stage including input cascode transistors and stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor. The input cascode transistors, the feedback transistor, and the stacked output transistors may include complementary metal-oxide semiconductor (CMOS) transistors.
Public/Granted literature
- US20160020780A1 Method And System For A Low Input Voltage Low Impedance Termination Stage For Current Inputs Public/Granted day:2016-01-21
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