Invention Grant
US09406516B2 High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor
有权
用于降低NMOS晶体管中的结漏电和接口陷阱的高K金属栅极工艺
- Patent Title: High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor
- Patent Title (中): 用于降低NMOS晶体管中的结漏电和接口陷阱的高K金属栅极工艺
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Application No.: US14680078Application Date: 2015-04-07
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Publication No.: US09406516B2Publication Date: 2016-08-02
- Inventor: Jian-Cun Ke , Chih-Wei Yang , Kun-Yuan Lo , Chia-Fu Hsu , Shao-Wei Wang
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/28 ; H01L29/49 ; H01L29/51 ; H01L29/78 ; H01L21/8238 ; H01L29/66 ; H01L29/165
Abstract:
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the substrate; forming a high-k dielectric layer on the interfacial layer; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer; performing a thermal treatment; removing the first BBM layer; and forming a second BBM layer on the high-k dielectric layer.
Public/Granted literature
- US20150214060A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2015-07-30
Information query
IPC分类:
