Invention Grant
US09406823B2 Methods for fabricating self-aligning semiconductor hetereostructures using nanowires
有权
使用纳米线制造自对准半导体hetereostructures的方法
- Patent Title: Methods for fabricating self-aligning semiconductor hetereostructures using nanowires
- Patent Title (中): 使用纳米线制造自对准半导体hetereostructures的方法
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Application No.: US14329748Application Date: 2014-07-11
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Publication No.: US09406823B2Publication Date: 2016-08-02
- Inventor: Andrew P. Homyk , Michael D. Henry , Axel Scherer , Sameer Walavalkar
- Applicant: CALIFORNIA INSTITUTE OF TECHNOLOGY
- Applicant Address: US CA Pasadena
- Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
- Current Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
- Current Assignee Address: US CA Pasadena
- Agency: Steinfl & Bruno LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L31/0352 ; B82Y10/00 ; H01L29/66 ; H01L29/775 ; H01L33/06 ; B82Y40/00 ; H01L29/12 ; H01L29/41 ; H01L21/02 ; H01L29/267

Abstract:
Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.
Public/Granted literature
- US20140319459A1 METHODS FOR FABRICATING SELF-ALIGNING SEMICONDUCTOR HETEREOSTRUCTURES USING NANOWIRES Public/Granted day:2014-10-30
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