Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.