Invention Grant
US09437706B2 Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
有权
使用保形沉积和热生长工艺制造金属 - 绝缘体 - 半导体隧穿触点的方法
- Patent Title: Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
- Patent Title (中): 使用保形沉积和热生长工艺制造金属 - 绝缘体 - 半导体隧穿触点的方法
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Application No.: US14552959Application Date: 2014-11-25
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Publication No.: US09437706B2Publication Date: 2016-09-06
- Inventor: Niloy Mukherjee , Gilbert Dewey , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L21/285 ; H01L21/768 ; H01L21/8234 ; H01L23/485 ; H01L29/08 ; H01L29/417 ; H01L29/45 ; H01L29/66 ; H01L29/78
Abstract:
A microelectronic device may be formed with at least one transistor having a source region and a drain region, wherein an interlayer dielectric layer may be formed adjacent the transistor. A trench may be formed through the first interlayer dielectric layer to at least one of the source region and the drain region and a conductive contact may be formed in the trench, wherein the conductive contact comprises a conformal conductive layer separated from the at least one of the source region and the drain region by a conformal insulating layer.
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