Invention Grant
US09442849B2 Apparatus and method for reduced core entry into a power state having a powered down core cache
有权
用于减少核心进入具有掉电核心高速缓存的电力状态的装置和方法
- Patent Title: Apparatus and method for reduced core entry into a power state having a powered down core cache
- Patent Title (中): 用于减少核心进入具有掉电核心高速缓存的电力状态的装置和方法
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Application No.: US13730915Application Date: 2012-12-29
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Publication No.: US09442849B2Publication Date: 2016-09-13
- Inventor: David Keppel , Kelvin Kwan , Jawad Nasrullah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Webster & Elliott, LLP
- Agent Nicholson De Vos
- Main IPC: G06F12/12
- IPC: G06F12/12 ; G06F12/08 ; G06F1/32
Abstract:
A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.
Public/Granted literature
- US20140189240A1 Apparatus and Method For Reduced Core Entry Into A Power State Having A Powered Down Core Cache Public/Granted day:2014-07-03
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