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    Handling of binary translated self modifying code and cross modifying code
    2.
    发明授权
    Handling of binary translated self modifying code and cross modifying code 有权
    处理二进制翻译自修改代码和交叉修改代码

    公开(公告)号：US09116729B2

    公开(公告)日：2015-08-25

    申请号：US13997694

    申请日：2012-12-27

    Applicant: Intel Corporation

    Inventor： Nirajan L. Cooray ,  David Keppel ,  Naveen Kumar ,  Ori Lempel ,  Michael Neilly ,  Naveen Neelakantam ,  H. Peter Anvin ,  Sebastian Winkel

    IPC: G06F9/455 ,  G06F12/10

    CPC classification number: G06F9/45525

    Abstract: A processor includes a processor core to execute a first translated instruction translated from a first instruction stored in first page of a memory. The processor also includes a translation indicator agent (XTBA) to store a first translation indicator that is read from a physical map (PhysMap) in the memory. In an embodiment, the first translation indicator is to indicate whether the first page has been modified after the first instruction is translated. Other embodiments are described as claimed.

    Abstract translation: 处理器包括处理器核，用于执行从存储在存储器的第一页中的第一指令转换的第一翻译指令。 处理器还包括翻译指示剂代理（XTBA），用于存储从存储器中的物理图（PhysMap）读取的第一翻译指示符。 在一个实施例中，第一翻译指示符是指示在第一指令被翻译之后第一页是否已被修改。 其他实施例被描述为所要求保护的。

    Symmetric addressing
    3.
    发明授权
    Symmetric addressing 有权

    公开(公告)号：US10331550B2

    公开(公告)日：2019-06-25

    申请号：US15282700

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： David Keppel ,  Charles J. Archer

    IPC: G06F13/00 ,  G06F12/02 ,  G06F12/1009

    Abstract: This disclosure describes, in one embodiment an apparatus. The apparatus includes a processor; a memory, an application, collector circuitry and aggregator circuitry. The memory is to store one or more tasks. The application is associated with the one or more tasks. The collector circuitry is to identify a local free address range in at least one address space. The aggregator circuitry is to provide address range data to a subgroup aggregator. The provided address range data includes at least one local free address range.

    Technologies for performance inspection at an endpoint node
    4.
    发明授权
    Technologies for performance inspection at an endpoint node 有权

    公开(公告)号：US10135708B2

    公开(公告)日：2018-11-20

    申请号：US14866536

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： James Dinan ,  David Keppel

    IPC: G06F15/173 ,  H04L12/26 ,  H04L29/08

    Abstract: Technologies for monitoring communication performance of a high performance computing (HPC) network include a performance probing engine of a source endpoint node of the HPC network. The performance probing engine is configured to generate a probe request that includes a timestamp of the probe request and transmit the probe request to a destination endpoint node of the HPC network communicatively coupled to the source endpoint node via the HPC network. The performance probing engine is additionally configured to receive a probe response from the destination endpoint node via the HPC network and to generate another timestamp that corresponds to the probe request having been received. Further, the performance probing engine is configured to determine a round-trip latency as a function of the probe request and probe response timestamps. Other embodiments are described and claimed.

    APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION
    5.
    发明申请
    APPARATUSES AND METHODS TO SELECTIVELY EXECUTE A COMMIT INSTRUCTION 审中-公开
    选择和方法选择执行委托指令

    公开(公告)号：US20160283247A1

    公开(公告)日：2016-09-29

    申请号：US14668605

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Girish Venkatasubramanian ,  Ethan Schuchman ,  David Keppel ,  Sebastian Winkel ,  David N. Mackintosh ,  Jaroslaw Topp

    IPC: G06F9/38

    CPC classification number: G06F9/30087 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/455 ,  G06F9/45516 ,  G06F9/4552

    Abstract: Methods and apparatuses relating to selectively executing a commit instruction. In one embodiment, a data storage device stores code that when executed by a hardware processor causes the hardware processor to perform the following: translating an instruction into a translated instruction to be executed by the hardware processor, marking a commit instruction one of for execution and for optional execution by the hardware processor, and including a hint for a commit instruction marked for optional execution; and a hardware commit unit to determine if the commit instruction marked for optional execution is to be executed based on the hint.

    Abstract translation: 与选择性地执行提交指令有关的方法和装置。 在一个实施例中，数据存储装置存储当硬件处理器执行时硬件处理器执行以下操作的代码：将指令转换成由硬件处理器执行的转换指令，标记提交指令以执行和 用于硬件处理器的可选执行，并且包括用于可选执行标记的提交指令的提示; 以及硬件提交单元，用于基于提示来确定标记为可选执行的提交指令是否被执行。

    Technologies for sideband performance tracing of network traffic
    6.
    发明授权
    Technologies for sideband performance tracing of network traffic 有权

    公开(公告)号：US10135711B2

    公开(公告)日：2018-11-20

    申请号：US14979140

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Robert C. Zak ,  David Keppel ,  James Dinan

    IPC: H04L12/26 ,  H04L12/721

    Abstract: Technologies for tracing network performance include a network computing device configured to receive a network packet from a source endpoint node, process the received network packet, capture trace data corresponding to the network packet as it is processed by the network computing device, and transmit the received network packet to a target endpoint node. The network computing device is further configured to generate a trace data network packet that includes at least a portion of the captured trace data and transmit the trace data network packet to the destination endpoint node. The destination endpoint node is configured to monitor performance of the network by reconstructing a trace of the network packet based on the trace data of the trace data network packet. Other embodiments are described herein.

    Technologies for aggregation-based message synchronization
    8.
    发明授权
    Technologies for aggregation-based message synchronization 有权

    公开(公告)号：US10178041B2

    公开(公告)日：2019-01-08

    申请号：US14862854

    申请日：2015-09-23

    Applicant: Intel Corporation

    Inventor： James Dinan ,  Mario Flajslik ,  David Keppel ,  Ulf R. Hanebutte

    IPC: H04L12/26 ,  H04L12/863 ,  H04L12/801 ,  H04L12/891 ,  H04L12/835

    Abstract: Technologies for aggregation-based message processing include multiple computing nodes in communication over a network. A computing node receives a message from a remote computing node, increments an event counter in response to receiving the message, determines whether an event trigger is satisfied in response to incrementing the counter, and writes a completion event to an event queue if the event trigger is satisfied. An application of the computing node monitors the event queue for the completion event. The application may be executed by a processor core of the computing node, and the other operations may be performed by a host fabric interface of the computing node. The computing node may be a target node and count one-sided messages received from an initiator node, or the computing node may be an initiator node and count acknowledgement messages received from a target node. Other embodiments are described and claimed.

    SYMMETRIC ADDRESSING
    9.
    发明申请
    SYMMETRIC ADDRESSING 审中-公开

    公开(公告)号：US20180217925A1

    公开(公告)日：2018-08-02

    申请号：US15282700

    申请日：2016-09-30

    Applicant: INTEL CORPORATION

    Inventor： David Keppel ,  Charles J. Archer

    IPC: G06F12/02

    CPC classification number: G06F12/023 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2212/1024 ,  G06F2212/656 ,  G06F2212/657

    Abstract: This disclosure describes, in one embodiment an apparatus. The apparatus includes a processor; a memory, an application, collector circuitry and aggregator circuitry. The memory is to store one or more tasks. The application is associated with the one or more tasks. The collector circuitry is to identify a local free address range in at least one address space. The aggregator circuitry is to provide address range data to a subgroup aggregator. The provided address range data includes at least one local free address range.

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