Invention Grant
- Patent Title: Uniform junction formation in FinFETs
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Application No.: US15054951Application Date: 2016-02-26
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Publication No.: US09466616B2Publication Date: 2016-10-11
- Inventor: Eric C. T. Harley , Judson R. Holt , Yue Ke , Timothy J. McArdle , Shogo Mochizuki , Alexander Reznicek
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agent Yuanmin Cai, Esq.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/78 ; H01L29/08 ; H01L29/06

Abstract:
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch FinFET devices, using recessed source-drain (S-D) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the S-D region is formed, may be used to control the profile and dopant concentration of the junction under the channel. In another embodiment, the profile and dopant concentration of the junction may be controlled via a dopant concentration gradient in the S-D region.
Public/Granted literature
- US20160181285A1 UNIFORM JUNCTION FORMATION IN FINFETS Public/Granted day:2016-06-23
Information query
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