Invention Grant
- Patent Title: Stress-reduced circuit board and method for forming the same
- Patent Title (中): 应力减小电路板及其形成方法
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Application No.: US13960897Application Date: 2013-08-07
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Publication No.: US09468091B2Publication Date: 2016-10-11
- Inventor: Chien-Cheng Wei , Wu-Hui Cheng
- Applicant: Chien-Cheng Wei , Wu-Hui Cheng
- Applicant Address: TW Taipei
- Assignee: Tong Hsing Electronic Industries, Ltd.
- Current Assignee: Tong Hsing Electronic Industries, Ltd.
- Current Assignee Address: TW Taipei
- Agency: Blank Rome LLP
- Priority: TW101138461A 20121018
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H05K3/06 ; H05K3/00 ; H05K1/03 ; H05K3/10 ; H05K3/14 ; H05K3/16 ; H05K3/38

Abstract:
A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.
Public/Granted literature
- US20140110159A1 STRESS-REDUCED CIRCUIT BOARD AND METHOD FOR FORMING THE SAME Public/Granted day:2014-04-24
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