公开(公告)号：US09468091B2

公开(公告)日：2016-10-11

申请号：US13960897

申请日：2013-08-07

Applicant: Chien-Cheng Wei ,  Wu-Hui Cheng

Inventor： Chien-Cheng Wei ,  Wu-Hui Cheng

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/00 ,  H05K1/03 ,  H05K3/10 ,  H05K3/14 ,  H05K3/16 ,  H05K3/38

CPC classification number: H05K1/0271 ,  H05K1/0265 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/108 ,  H05K3/146 ,  H05K3/16 ,  H05K3/388 ,  H05K2201/0338 ,  H05K2201/09845 ,  H05K2203/058 ,  H05K2203/1476 ,  H05K2203/1572

Abstract: A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.

Abstract translation: 应力降低电路板包括绝缘基板以及彼此堆叠的第一和第二导电层，并且分别具有以阶梯式布置的周边边缘区域。 第一导电层被配置为具有比第二导电层的面积尺寸更大的面积尺寸，并且其厚度不大于第二导电层的厚度，以便使由于第二导电层之间的热膨胀系数的差异而引起的应力最小化 绝缘基板和第一和第二导电层。

公开(公告)号：US20140110159A1

公开(公告)日：2014-04-24

申请号：US13960897

申请日：2013-08-07

Applicant: Chien-Cheng Wei ,  Wu-Hui Cheng

Inventor： Chien-Cheng Wei ,  Wu-Hui Cheng

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/00

CPC classification number: H05K1/0271 ,  H05K1/0265 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/108 ,  H05K3/146 ,  H05K3/16 ,  H05K3/388 ,  H05K2201/0338 ,  H05K2201/09845 ,  H05K2203/058 ,  H05K2203/1476 ,  H05K2203/1572

Abstract: A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.

Abstract translation: 应力降低电路板包括绝缘基板以及彼此堆叠的第一和第二导电层，并且分别具有以阶梯式布置的周边边缘区域。 第一导电层被配置为具有比第二导电层的面积尺寸更大的面积尺寸，并且其厚度不大于第二导电层的厚度，以便使由于第二导电层之间的热膨胀系数的差异而引起的应力最小化 绝缘基板和第一和第二导电层。