Invention Grant
- Patent Title: Pattern suppression in logic for wafer inspection
- Patent Title (中): 晶圆检查逻辑中的图案抑制
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Application No.: US14682822Application Date: 2015-04-09
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Publication No.: US09506873B2Publication Date: 2016-11-29
- Inventor: Vaibhav Gaind , Nisha Amthul
- Applicant: KLA-Tencor Corporation
- Applicant Address: US CA Milpitas
- Assignee: KLA-Tencor Corp.
- Current Assignee: KLA-Tencor Corp.
- Current Assignee Address: US CA Milpitas
- Agent Ann Marie Mewherter
- Main IPC: G01N21/00
- IPC: G01N21/00 ; G01N21/95 ; G01N21/956

Abstract:
Methods and systems for detecting defects on a wafer are provided. One system includes an illumination subsystem configured to direct light to at least one spot on a wafer. The system also includes at least one element configured to block first portion(s) of light scattered from the at least one spot from reaching a detector while allowing second portion(s) of the light scattered from the at least one spot to be detected by the detector. The first portion(s) of the light are scattered from one or more patterned features in a logic region on the wafer. The second portion(s) of the light are not scattered from the one or more patterned features. The detector is not an imaging detector. The system further includes a computer subsystem configured to detect defects on the wafer based on output of the detector.
Public/Granted literature
- US20150293035A1 Pattern Suppression in Logic for Wafer Inspection Public/Granted day:2015-10-15
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