Invention Grant
US09535126B2 Tap, test, CSU, scan circuitry with top and bottom contacts
有权
点击，测试，CSU，具有顶部和底部触点的扫描电路
- Patent Title: Tap, test, CSU, scan circuitry with top and bottom contacts
- Patent Title (中): 点击，测试，CSU，具有顶部和底部触点的扫描电路
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Application No.: US15206973Application Date: 2016-07-11
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Publication No.: US09535126B2Publication Date: 2017-01-03
- Inventor: Lee D. Whetsel
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/3185 ; G01R31/28 ; G01R31/3183
Abstract:
This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.
Public/Granted literature
- US20160322270A1 3D TAP & SCAN PORT ARCHITECTURES Public/Granted day:2016-11-03
Information query
