Disclosed is a multi-core processor that includes a processor core, a graphics core, and a cache controller. The cache controller receives a first request from an input-output (I/O) device to lock a first address that corresponds to a way in a first set of ways in a cache. The cache controller sends, to the I/O device, a rejection of the first request when the way in the first set is not lockable for the I/O device. The cache controller receives a second request from the I/O device to lock a second address that corresponds to a way in a second set of ways in the cache. The cache controller locks the way in the second set in response to the second request.