Invention Grant
- Patent Title: Trap rich layer with through-silicon-vias in semiconductor devices
- Patent Title (中): 在半导体器件中通过硅通孔捕获富层
-
Application No.: US14043764Application Date: 2013-10-01
-
Publication No.: US09558951B2Publication Date: 2017-01-31
- Inventor: Anton Arriagada , Chris Brindle , Michael A. Stuber
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L21/302 ; H01L21/20 ; H01L21/762 ; H01L21/768 ; H01L21/84 ; H01L23/48 ; H01L23/522 ; H01L27/12 ; H01L29/78

Abstract:
An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.
Public/Granted literature
- US20140030871A1 Trap Rich Layer with Through-Silicon-Vias in Semiconductor Devices Public/Granted day:2014-01-30
Information query
IPC分类: