公开(公告)号：US09530796B2

公开(公告)日：2016-12-27

申请号：US14272261

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber ,  Stuart B. Molin ,  Chris Brindle

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit assembly comprises an insulating layer, a semiconductor layer, a handle layer, a metal interconnect layer, and transistors. The insulating layer has a first surface, a second surface, and a hole extending from the first surface to the second surface. The semiconductor layer has a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer. The handle layer is coupled to the second surface of the semiconductor layer. The metal interconnect layer is coupled to the second surface of the insulating layer, the metal interconnect layer being disposed within the hole in the insulating layer. The transistors are located in the semiconductor layer. The hole in the insulating layer extends to at least the first surface of the semiconductor layer. The metal interconnect layer electrically couples a plurality of the transistors to each other.

Abstract translation: 集成电路组件包括绝缘层，半导体层，手柄层，金属互连层和晶体管。 绝缘层具有第一表面，第二表面和从第一表面延伸到第二表面的孔。 半导体层具有第一表面和第二表面，半导体层的第一表面与绝缘层的第一表面接触。 手柄层耦合到半导体层的第二表面。 金属互连层耦合到绝缘层的第二表面，金属互连层设置在绝缘层的孔内。 晶体管位于半导体层中。 绝缘层中的孔至少延伸到半导体层的第一表面。 金属互连层将多个晶体管彼此电耦合。

公开(公告)号：US09558951B2

公开(公告)日：2017-01-31

申请号：US14043764

申请日：2013-10-01

Applicant: QUALCOMM Incorporated

Inventor： Anton Arriagada ,  Chris Brindle ,  Michael A. Stuber

IPC: H01L21/46 ,  H01L21/302 ,  H01L21/20 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/302 ,  H01L21/2007 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/80001 ,  H01L2224/9202

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract translation: 集成电路芯片形成有电路层，阱富层和贯通半导体通孔。 陷阱富层形成在电路层上。 贯通半导体通孔也形成在电路层的上方。 在一些实施例中，电路层被包括在晶片中，并且阱富层和贯穿半导体通孔被包括在另一个晶片中。 在形成富集陷阱层和通过半导体通孔之后，两个晶片结合在一起。 另外，在一些实施例中，另一个晶片也可以结合到晶片上，该晶片包括陷阱富集层和贯穿半导体通路。 此外，在一些实施例中，可以在晶片中形成另外的电路层，其中包括阱富层和贯通半导体通路。