Invention Grant
- Patent Title: Load balancing and merging of tessellation thread workloads
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Application No.: US14625528Application Date: 2015-02-18
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Publication No.: US09607353B2Publication Date: 2017-03-28
- Inventor: Yunjiu Li , Michael Green
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06T1/20
- IPC: G06T1/20 ; G06T17/20 ; G06T15/80

Abstract:
In one embodiment described herein, a graphics engine with shader unit thread load balancing functionality executes shader instructions from multiple execution threads in a smaller number of execution threads by combining instructions from multiple threads at runtime. In one embodiment, multiple shader unit threads containing less than a minimum number of instructions are combined to minimize the discrepancy between the shortest and longest thread. In one embodiment, threads are merged when they contain a common output register.
Public/Granted literature
- US20150161757A1 LOAD BALANCING AND MERGING OF TESSELLATION THREAD WORKLOADS Public/Granted day:2015-06-11
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