A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.