Invention Grant
- Patent Title: High performance interconnect physical layer
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Application No.: US14538871Application Date: 2014-11-12
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Publication No.: US09612986B2Publication Date: 2017-04-04
- Inventor: Venkatraman Iyer , Darren S. Jue , Sitaraman Iyer
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Patent Capital Group
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/40 ; G06N99/00
Abstract:
A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
Public/Granted literature
- US20150067210A1 HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER Public/Granted day:2015-03-05
Information query
