A semiconductor memory device for high speed operation, and for flexible data reading and programming is disclosed. The flash memory of the present disclosure includes: a page buffer/sensor circuit including a volatile memory element that may maintain data with a size corresponding to a page of a memory array; a high speed cache register including a non-volatile memory element that may maintain data with a size corresponding to a page of a memory array. The page buffer/sensor circuit includes a sensor circuit, a data register, and a transmission gate. The data register may transmit and receive data with an input-output buffer. The high speed cache register includes RRAM, wherein the RRAM may transmit and receive data with an input-output buffer via a transmission gate, and may transmit and receive data with the data register via a transmission gate.