Invention Grant
- Patent Title: Full/reduced pin JTAG interface shadow protocol detection, command, address circuits
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Application No.: US15159171Application Date: 2016-05-19
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Publication No.: US09645198B2Publication Date: 2017-05-09
- Inventor: Lee D. Whetsel
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/28 ; G01R31/302 ; G01R31/3185 ; G01R31/317

Abstract:
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
Public/Granted literature
- US20160259003A1 INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES Public/Granted day:2016-09-08
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