A semiconductor device fabrication process includes forming a fin and a plurality of gates upon a semiconductor substrate, forming sacrificial spacers upon opposing gate sidewalls, forming a mask upon an upper surface of the fin between neighboring gates, removing the sacrificial spacers, recessing a plurality of regions of the fin to create a dummy fin and fin segments, removing the mask, and epitaxially merging the dummy fin and fin segments. The fins may be partially recessed prior to forming the sacrificial spacers. The device may include the substrate, gates, fin segments each associated with a particular gate, the dummy fin between a fin segment pair separated by the wider pitch, and merged epitaxy connecting the dummy fin and the fin segment pair. The dummy fin may serve as a filler between the fin segment pair and may add epitaxial growth planes to allow for epitaxial merging within the wider pitch.