Invention Grant
- Patent Title: Method of manufacturing an insulated gate bipolar transistor with mesa sections between cell trench structures
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Application No.: US14734723Application Date: 2015-06-09
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Publication No.: US09653568B2Publication Date: 2017-05-16
- Inventor: Johannes Georg Laven , Alexander Philippou , Hans-Joachim Schulze , Christian Jaeger , Roman Baburske , Antonio Vellei
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/66 ; H01L29/739 ; H01L21/223 ; H01L21/265 ; H01L21/266

Abstract:
A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.
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