公开(公告)号：US20230352531A1

公开(公告)日：2023-11-02

申请号：US18220989

申请日：2023-07-12

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Christian Jaeger ,  Moriz Jelinek ,  Daniel Schloegl ,  Benedikt Stoib

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/322 ,  H01L29/10

CPC classification number: H01L29/0834 ,  H01L29/7395 ,  H01L29/0638 ,  H01L29/66333 ,  H01L21/26513 ,  H01L21/3221 ,  H01L29/1095

Abstract: A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.

公开(公告)号：US11594621B2

公开(公告)日：2023-02-28

申请号：US17087678

申请日：2020-11-03

Applicant: Infineon Technologies AG

Inventor： Antonio Vellei ,  Markus Beninger-Bina ,  Matteo Dainese ,  Christian Jaeger ,  Johannes Georg Laven ,  Alexander Philippou ,  Francisco Javier Santos Rodriguez

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/40 ,  H01L21/033 ,  H01L21/225 ,  H01L21/265 ,  H01L21/324 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A method of processing a power semiconductor device includes: providing a semiconductor body with a drift region of a first conductivity type; forming a plurality of trenches extending into the semiconductor body along a vertical direction and arranged adjacent to each other along a first lateral direction; providing a mask arrangement at the semiconductor body, the mask arrangement having a lateral structure according to which some of the trenches are exposed and at least one of the trenches is covered by the mask arrangement along the first lateral direction; forming, below bottoms of the exposed trenches, a plurality of doping regions of a second conductivity type complementary to the first conductivity type; removing the mask arrangement; and extending the plurality of doping regions in parallel to the first lateral direction such that the plurality of doping regions overlap and form a barrier region of the second conductivity type adjacent to the bottoms of the exposed trenches.

公开(公告)号：US20210320174A1

公开(公告)日：2021-10-14

申请号：US17217251

申请日：2021-03-30

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Christian Jaeger ,  Moriz Jelinek ,  Daniel Schloegl ,  Benedikt Stoib

IPC: H01L29/08 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L21/322 ,  H01L29/66

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.

公开(公告)号：US10347754B2

公开(公告)日：2019-07-09

申请号：US15704269

申请日：2017-09-14

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Christian Jaeger ,  Johannes Georg Laven ,  Max Christian Seifert ,  Antonio Vellei

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/66 ,  H01L29/739 ,  H01L29/866

Abstract: A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load terminal and comprising a drift region configured to conduct a load current between said terminals. The drift region comprises dopants of a first conductivity type. A source region is arranged in electrical contact with the first load terminal and comprises dopants of the first conductivity type. A channel region comprises dopants of a second conductivity. At least one power unit cell that includes at least one first type trench. The at least one power unit cell further includes a first mesa zone and a second mesa zone of the semiconductor body.

公开(公告)号：US10096531B2

公开(公告)日：2018-10-09

申请号：US14861569

申请日：2015-09-22

Applicant: Infineon Technologies AG

Inventor： Christian Jaeger ,  Johannes Georg Laven ,  Frank Dieter Pfirsch ,  Alexander Philippou

IPC: H01L21/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40

Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region. The semiconductor device further includes: a first load contact structure included in the surface region and arranged for feeding a load current into the semiconductor body region; a first trench extending into the semiconductor body region and having a sensor electrode and a first dielectric, the first dielectric electrically insulating the sensor electrode from the second semiconductor region; an electrically conductive path electrically connecting the sensor electrode to the first semiconductor region; a first semiconductor path, wherein the first semiconductor region is electrically coupled to the first load contact structure by at least the first semiconductor path; a sensor contact structure included in the surface region and arranged for receiving an electrical potential of the sensor electrode.

公开(公告)号：US20160118382A1

公开(公告)日：2016-04-28

申请号：US14986166

申请日：2015-12-31

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Christian Jaeger ,  Hans-Joachim Schulze

IPC: H01L27/06 ,  H01L29/66

CPC classification number: H01L27/0664 ,  H01L21/04 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/66143 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7397

Abstract: A reverse blocking semiconductor device is manufactured by introducing impurities of a first conductivity type into a semiconductor substrate of the first conductivity type through a process surface to obtain a process layer extending into the semiconductor substrate up to a first depth, and introducing impurities of a second, complementary conductivity type into the semiconductor substrate through openings of an impurity mask provided on the process surface to obtain emitter zones of the second conductivity type extending up to a second depth deeper than the first depth and channels of the first conductivity type between the emitter zones. Exposed portions of the process layer are removed above the emitter zones.

Abstract translation: 反向阻挡半导体器件通过将第一导电类型的杂质通过工艺表面引入第一导电类型的半导体衬底而制造，以获得延伸到半导体衬底中的工艺层直到第一深度，并且引入第二导电类型的杂质 通过设置在工艺表面上的杂质掩模的开口将半导体衬底的互补导电类型引入半导体衬底，以获得第二导电类型的发射区延伸到比第一深度更深的第二深度，并且在发射极区之间具有第一导电类型的沟道 。 处理层的暴露部分在发射区之上被去除。

公开(公告)号：US09105679B2

公开(公告)日：2015-08-11

申请号：US14091955

申请日：2013-11-27

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Christian Jaeger

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/861

CPC classification number: H01L29/7397 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/8613

Abstract: In a semiconductor device a barrier region is sandwiched between a drift region and a charge carrier transfer region. The barrier and charge carrier transfer regions form a pn junction. The barrier and drift regions form a homojunction. A mean impurity concentration in the barrier region is at least ten times as high as an impurity concentration in the drift region. A control structure is arranged to form an inversion layer in the drift and barrier regions in an inversion state. No inversion layer is formed in the drift and barrier regions in a non-inversion state.

Abstract translation: 在半导体器件中，阻挡区域夹在漂移区域和电荷载流子传输区域之间。 势垒和电荷载流子转移区形成pn结。 屏障和漂移区域形成同质结。 阻挡区域中的平均杂质浓度为漂移区域的杂质浓度的至少十倍。 控制结构被布置成在反转状态下在漂移和阻挡区域中形成反型层。 在非反转状态下，在漂移区和阻挡区中不形成反转层。

公开(公告)号：US20150144988A1

公开(公告)日：2015-05-28

申请号：US14091955

申请日：2013-11-27

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Christian Jaeger

IPC: H01L29/739 ,  H01L29/861 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7396 ,  H01L29/8613

Abstract: In a semiconductor device a barrier region is sandwiched between a drift region and a charge carrier transfer region. The barrier and charge carrier transfer regions form a pn junction. The barrier and drift regions form a homojunction. A mean impurity concentration in the barrier region is at least ten times as high as an impurity concentration in the drift region. A control structure is arranged to form an inversion layer in the drift and barrier regions in an inversion state. No inversion layer is formed in the drift and barrier regions in a non-inversion state.

Abstract translation: 在半导体器件中，阻挡区域夹在漂移区域和电荷载流子传输区域之间。 势垒和电荷载流子转移区形成pn结。 屏障和漂移区域形成同质结。 阻挡区域中的平均杂质浓度为漂移区域的杂质浓度的至少十倍。 控制结构被布置成在反转状态下在漂移和阻挡区域中形成反型层。 在非反转状态下，在漂移区和阻挡区中不形成反转层。

公开(公告)号：US20150076554A1

公开(公告)日：2015-03-19

申请号：US14026383

申请日：2013-09-13

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Alexander Philippou ,  Hans-Joachim Schulze ,  Christian Jaeger ,  Roman Baburske ,  Antonio Vellei

IPC: H01L29/739 ,  H01L29/66

CPC classification number: H01L29/66348 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7397

Abstract: An IGBT includes a mesa section that extends between two cell trench structures from a first surface of a semiconductor portion to a layer section of the semiconductor portion. A source region, which is electrically connected to an emitter electrode, is formed in the mesa section. A doped region, which is separated from the source region by a body region of a complementary conductivity type, includes a first portion with a first mean net impurity concentration and a second portion with a second mean net impurity concentration exceeding at least ten times the first mean net impurity concentration. In the mesa section the first portion extends from the body region to the layer section. The second portions of the doped region virtually narrow the mesa sections in a normal on-state of the IGBT.

Abstract translation: IGBT包括从半导体部分的第一表面到半导体部分的层部分的两个电池沟槽结构之间延伸的台面部分。 在台面部分形成有与发射电极电连接的源极区域。 通过互补导电类型的体区与源极区分离的掺杂区包括具有第一平均净杂质浓度的第一部分和具有超过第一平均净杂质浓度的至少十倍的第二平均净杂质浓度的第二部分 平均净杂质浓度。 在台面部分中，第一部分从身体区域延伸到层部分。 掺杂区域的第二部分在IGBT的正常导通状态下实际上使台面部分变窄。

公开(公告)号：US20140209973A1

公开(公告)日：2014-07-31

申请号：US13754943

申请日：2013-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Christian Jaeger ,  Hans-Joachim Schulze

IPC: H01L29/739 ,  H01L21/04

CPC classification number: H01L27/0664 ,  H01L21/04 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/66143 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7397

Abstract: A reverse blocking semiconductor device includes a base region of a first conductivity type and a body region of a second, complementary conductivity type, wherein the base and body regions form a pn junction. Between the base region and a collector electrode an emitter layer is arranged that includes emitter zones of the second conductivity type and at least one channel of the first conductivity type. The channels extend through the emitter layer between the base region and the collector electrode and reduce the leakage current in a forward blocking state.

Abstract translation: 反向阻挡半导体器件包括第一导电类型的基极区域和第二互补导电类型的体区域，其中基极区域和主体区域形成pn结。 在基极区域和集电极电极之间布置发射极层，其包括第二导电类型的发射区和至少一个第一导电类型的沟道。 通道延伸穿过基极区域和集电极之间的发射极层，并且在正向阻挡状态下减小漏电流。