Invention Grant
- Patent Title: III-N transistors with enhanced breakdown voltage
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Application No.: US15120705Application Date: 2014-03-26
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Publication No.: US09666708B2Publication Date: 2017-05-30
- Inventor: Han Wui Then , Benjamin Chu-Kung , Sansaptak Dasgupta , Robert S. Chau , Seung Hoon Sung , Ravi Pillarisetty , Marko Radosavljevic
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- International Application: PCT/US2014/031903 WO 20140326
- International Announcement: WO2015/147816 WO 20151001
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/66 ; H01L29/20 ; H01L21/8252 ; H01L27/06 ; H01L21/02 ; H01L21/033 ; H01L29/08 ; H01L29/205
Abstract:
Techniques related to III-N transistors having enhanced breakdown voltage, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include a hardmask having an opening over a substrate, a source, a drain, and a channel between the source and drain, and a portion of the source or the drain disposed over the opening of the hardmask.
Public/Granted literature
- US20170018640A1 III-N TRANSISTORS WITH ENHANCED BREAKDOWN VOLTAGE Public/Granted day:2017-01-19
Information query
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