Invention Grant
- Patent Title: Integration of III-V devices on Si wafers
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Application No.: US14908112Application Date: 2013-09-27
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Publication No.: US09673045B2Publication Date: 2017-06-06
- Inventor: Sansaptak Dasgupta , Han Wui Then , Seung Hoon Sung , Sanaz K. Gardner , Marko Radosavljevic , Benjamin Chu-Kung , Robert S. Chau
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- International Application: PCT/US2013/062481 WO 20130927
- International Announcement: WO2015/047355 WO 20150402
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/02 ; H01L21/8258 ; H01L29/20 ; H01L29/205 ; H01L29/778
Abstract:
An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.
Public/Granted literature
- US20160181085A1 INTEGRATION OF III-V DEVICES ON SI WAFERS Public/Granted day:2016-06-23
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