Aspects and embodiments are directed to a digital unit cell comprising an integrator circuit, a dynamic comparator configured to compare an integration voltage of the integrator circuit with a reference voltage, provide a first pulse signal each time the integration voltage is less than the reference voltage, and provide a second pulse signal each time the integration voltage exceeds the reference voltage, a multiplexer configured to receive a count direction control signal, and a counter element configured to increment a count value each time the first pulse signal or the second pulse signal is received, wherein the multiplexer is configured to couple a first output of the dynamic comparator to the counter element when the count direction control signal is in a first state, and to couple a second output of the dynamic comparator to the counter element when the count direction control signal is in a second state.