Invention Grant
- Patent Title: Semiconductor test structure for MOSFET noise testing
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Application No.: US14403565Application Date: 2013-09-04
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Publication No.: US09685386B2Publication Date: 2017-06-20
- Inventor: Xiaodong He
- Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
- Applicant Address: CN Jiangsu
- Assignee: CSME TECHNOLOGIES FAB1 CO., LTD.
- Current Assignee: CSME TECHNOLOGIES FAB1 CO., LTD.
- Current Assignee Address: CN Jiangsu
- Agency: Nixon Peabody, LLP
- Agent Khaled Shami
- Priority: CN201210406422 20121023
- International Application: PCT/CN2013/082910 WO 20130904
- International Announcement: WO2014/063533 WO 20140501
- Main IPC: H01L23/552
- IPC: H01L23/552 ; H01L21/66 ; H01L29/78 ; H01L23/522

Abstract:
The present invention provides a semiconductor test structure for MOSFET noise testing. The semiconductor test structure includes: a MOSFET device having a first conductivity type formed on a first well region of a semiconductor substrate; a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device and extending beyond the circumference of the first well region; a deep well region having a second conductivity type formed in the semiconductor substrate close to the bottom surface of the first well region, the deep well region extending beyond the circumference of the first well region; wherein a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region. The metal shielding layer is used to be connected to the ground terminal of a testing machine during testing, and the first conductivity type and the second conductivity type are opposite conductivity types.
Public/Granted literature
- US20150221568A1 Semiconductor Test Structure For Mosfet Noise Testing Public/Granted day:2015-08-06
Information query
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