A product synthesizer has a core CPU, power distribution, and a plurality of selectable interfaces, each interface having an associated schematic symbol, PCB symbol, mechanical model, power dissipation, and power requirement. A set of constraints identifies performance metrics including low power, high performance, battery or mains power, battery life, and other constraints. The product synthesizer receives as inputs the interfaces and constraints, and generates as outputs a schematic diagram, a bill of materials, a routed printed circuit board, and a solid model of an enclosure, all of which satisfy the constraints and include the identified interfaces.