Invention Grant
- Patent Title: Reduced PTH pad for enabling core routing and substrate layer count reduction
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Application No.: US14963215Application Date: 2015-12-08
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Publication No.: US09711441B2Publication Date: 2017-07-18
- Inventor: Debendra Mallik , Mihir Roy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Winkle, PLLC
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L23/48 ; H01L23/498 ; H01L21/48 ; H05K1/11
Abstract:
Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
Public/Granted literature
- US20160155694A1 REDUCED PTH PAD FOR ENABLING CORE ROUTING AND SUBSTRATE LAYER COUNT REDUCTION Public/Granted day:2016-06-02
Information query
IPC分类:
