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1.发明申请REDUCED PTH PAD FOR ENABLING CORE ROUTING AND SUBSTRATE LAYER COUNT REDUCTION 审中-公开减少PTH垫，用于启用核心路由和基板层数减少公开(公告)号：US20160155694A1
公开(公告)日：2016-06-02
申请号：US14963215
申请日：2015-12-08
Applicant: Intel Corporation
Inventor： Debendra Mallik , Mihir Roy
IPC: H01L23/498 , H05K1/11
CPC classification number: H01L23/49827 , H01L21/4857 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L2224/16225 , H05K1/113 , H05K1/115
Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
Abstract translation: 实施例涉及具有减小尺寸的电镀通孔（PTH）焊盘的半导体封装，通过消除焊盘到PTH对准的边缘并且使得能够在衬底的芯上更细的迹线。
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公开(公告)号：US09711441B2
公开(公告)日：2017-07-18
申请号：US14963215
申请日：2015-12-08
Applicant: Intel Corporation
Inventor： Debendra Mallik , Mihir Roy
IPC: H01L23/52 , H01L23/48 , H01L23/498 , H01L21/48 , H05K1/11
CPC classification number: H01L23/49827 , H01L21/4857 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L2224/16225 , H05K1/113 , H05K1/115
Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.
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