A resistive memory apparatus including a resistive memory cell array and a control unit is provided. The resistive memory cell array includes resistive memory cells. The control unit is configured to receive a logic data, determine a logic level of the logic data, and select one resistive memory cell from the resistive memory cells. The control unit provides a set signal or a reset signal to the selected resistive memory cell in a writing period according to the logic level of the logic data. The set signal includes a first set pulse and a second set pulse having a polarity opposite to that of the first set pulse. The reset signal includes a first reset pulse and a second reset pulse having a polarity opposite to that of the first reset pulse. A writing method of the resistive memory apparatus is also provided.