Invention Grant
- Patent Title: Systems and methods for supporting a plurality of load and store accesses of a cache
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Application No.: US14922035Application Date: 2015-10-23
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Publication No.: US09720839B2Publication Date: 2017-08-01
- Inventor: Karthikeyan Avudaiyappan , Mohammad Abdallah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0846 ; G06F12/0895

Abstract:
Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.
Public/Granted literature
- US20160041913A1 SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD AND STORE ACCESSES OF A CACHE Public/Granted day:2016-02-11
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