Invention Grant
- Patent Title: Tap dual port router circuitry with gated shiftDR and clockDR
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Application No.: US15340507Application Date: 2016-11-01
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Publication No.: US09753085B2Publication Date: 2017-09-05
- Inventor: Lee D. Whetsel
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/3185 ; G01R31/317
Abstract:
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
Public/Granted literature
- US20170045581A1 3D STACKED DIE TEST ARCHITECTURE Public/Granted day:2017-02-16
Information query
