Invention Grant
- Patent Title: Performing local power gating in a processor
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Application No.: US14960887Application Date: 2015-12-07
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Publication No.: US09772674B2Publication Date: 2017-09-26
- Inventor: Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F9/30 ; G06F9/38
Abstract:
In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
Public/Granted literature
- US20160085287A1 Performing Local Power Gating In A Processor Public/Granted day:2016-03-24
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