A memory control circuit unit, a memory storage device and a data transmitting method are provided. The memory storage device coupled to a first host system includes a reset pin. The memory control circuit unit of the memory storage device includes a pulse pattern detector. The reset pin is coupled to a second host system and is configured to receive a first pulse signal from the second host system. The pulse pattern detector is coupled to the reset pin, and is configured to determine whether the first pulse signal is conformed to a first predetermined serial pulse pattern or not. If the first pulse signal is conformed to the first predetermined serial pulse pattern, the memory control circuit unit is configured to disable a reset function of the memory storage device.