Invention Grant
- Patent Title: Memory erasure information in cache lines
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Application No.: US15034651Application Date: 2013-12-09
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Publication No.: US09778982B2Publication Date: 2017-10-03
- Inventor: Lidia Warnes , Erin A Handgen , Andrew C. Walton
- Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Applicant Address: US TX Houston
- Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee Address: US TX Houston
- Agency: Hewlett Packard Enterprise Patent Department
- International Application: PCT/US2013/073871 WO 20131209
- International Announcement: WO2015/088476 WO 20150618
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G06F11/16 ; G06F12/0811 ; G06F12/0831 ; G06F12/0893 ; G06F12/128 ; G06F12/0875 ; G06F11/20

Abstract:
Example implementations relate to storing memory erasure information in memory devices on a memory module. In example implementations, a memory location associated with an error in a first cache line may be identified. The first cache line may include data read from the memory location, and the memory location may be in a first memory device of a plurality of memory devices on a memory module. A device number corresponding to the first memory device may be written to one of the plurality of memory devices. When the memory location is read for a second cache line, the device number corresponding to the first memory device may be retrieved. The second cache line may include the retrieved device number and data read from the memory location.
Public/Granted literature
- US20160274968A1 MEMORY ERASURE INFORMATION IN CACHE LINES Public/Granted day:2016-09-22
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