Invention Grant
- Patent Title: Simultaneous and selective wide gap partitioning of via structures using plating resist
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Application No.: US14205331Application Date: 2014-03-11
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Publication No.: US09781844B2Publication Date: 2017-10-03
- Inventor: Shinichi Iketani , Dale Kersten
- Applicant: SANMINA CORPORATION
- Applicant Address: US CA San Jose
- Assignee: SANMINA CORPORATION
- Current Assignee: SANMINA CORPORATION
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Julio Loza
- Main IPC: H05K3/42
- IPC: H05K3/42 ; H05K1/11 ; H05K1/02

Abstract:
A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
Public/Granted literature
- US20140262455A1 SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST Public/Granted day:2014-09-18
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