Cache logic generates a cache address from an input memory address that includes a first binary string and a second binary string. The cache logic includes a hashing engine configured to generate a third binary string from the first binary string and to form each bit of the third binary string by combining a respective subset of bits of the first binary string by a first bitwise operation, wherein the subsets of bits of the first binary string are defined at the hashing engine such that each subset is unique and comprises approximately half of the bits of the first binary string; and a combination unit arranged to combine the third binary string with the second binary string by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.